FPGA Implementation of Parallel Fast Fourier Transform

Abstract

The Fast Fourier Transform (FFT) is a fundamental signal processing technique. FFT implementations with high throughput are required by modern higher-speed signal processing and communications protocols such as 4G LTE, 5G, the Internet of Things (IoT), and so on. Furthermore, the FFT resolution mandated by the preceding standards differs depending on the mode of operation. As a result, it’s highly desired to own an FFT implementation which not just supports the high throughput requirement, but additionally expandable to handle any configurable N point FFT resolution. This study simulates and implements the Parallel 256-point radix-2 Fast Fourier Transform. The Parallel FFT technique improves system performance and makes it faster. The simulation was carried out in MATLAB (version R2023b), and the implementation was carried out in the Virtex 6 XC6VLX240T FPGA kit using VHDL codes written in the Xilinx package version 14.7, with ModelSim (version SE-64 10.6d) used to present the simulation results.